1. Field of the Invention
This invention relates to computer system memories. In particular, this invention relates to a write-through operation involving a lower-level memory and a higher-level memory which skips at least one intermediate-level of memory in a computer system.
2. Description of the Related Art
In a typical multi-level-cache multi-node computer system having first-level caches (L1$s), second-level caches (L2$s) and a third level caches (L3$s), within each node, inclusion is maintained between the L1$s and the L2$s, but inclusion is not required between the L2$s and the L3$s. In other words, data that resides in a L1$ also resides in a respective L2$. However, data residing in the L1$ or L2$ do not necessarily have to reside in a respective L3$.
The L2$s are generally designated as copy-back caches because as second level caches, the L2$s can generate too much network traffic operating as write-through caches. Intuitively, the L3$s should also be designated as copy-back caches because the L3$s are higher level and larger than both the L2$s and the L1$s.
When data is first accessed by a requesting processor, the data is fetched from its home location and automatically cached in the respective L1$ and L2$. Subsequently, if the requesting processor writes/modifies the data, copies of the data in both the L1$ and L2$ are updated, i.e., write through is performed between the L1$ and the L2$.
However, since the L2$ is a copyback cache, changes in the L2$ are not immediately reflected in the home location of the data nor in the L3$, regardless of whether a copy of the data also exist in the L3$. A subsequent writeback transaction is used to update the data to its home location when dirty data in the L2$ needs replacement. Similarly, since the L3$ associated with requesting processor is also a copy-back cache, no immediate write back is initiated between the L3$ and the data's home location.
The perceived efficiency of the above described scheme is based on the assumption that any advantage gained by enforcing write-through protocol for either the L2$ and/or L3$ is far outweighed by a drastic increase in network traffic. However, the complexity of implementing a copy-back L3$ and the fact that a copy-back L2$ will already avoid most of the extra traffic in the network begs for simpler and more efficient solutions.
Hence, there is a need for a flexible scheme to efficiently designate memory write-back protocols for the multiple levels of memories within a computer system. Such a scheme should accomplish data coherency within the computer system without imposing an undue burden on the underlying network of the computer system.